miasm
Reverse engineering framework
JitCore_ppc32_regs.h
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1 JITCORE_PPC_REG_EXPAND(R0, 32)
2 JITCORE_PPC_REG_EXPAND(R1, 32)
3 JITCORE_PPC_REG_EXPAND(R2, 32)
4 JITCORE_PPC_REG_EXPAND(R3, 32)
5 JITCORE_PPC_REG_EXPAND(R4, 32)
6 JITCORE_PPC_REG_EXPAND(R5, 32)
7 JITCORE_PPC_REG_EXPAND(R6, 32)
8 JITCORE_PPC_REG_EXPAND(R7, 32)
9 JITCORE_PPC_REG_EXPAND(R8, 32)
10 JITCORE_PPC_REG_EXPAND(R9, 32)
11 JITCORE_PPC_REG_EXPAND(R10, 32)
12 JITCORE_PPC_REG_EXPAND(R11, 32)
13 JITCORE_PPC_REG_EXPAND(R12, 32)
14 JITCORE_PPC_REG_EXPAND(R13, 32)
15 JITCORE_PPC_REG_EXPAND(R14, 32)
16 JITCORE_PPC_REG_EXPAND(R15, 32)
17 JITCORE_PPC_REG_EXPAND(R16, 32)
18 JITCORE_PPC_REG_EXPAND(R17, 32)
19 JITCORE_PPC_REG_EXPAND(R18, 32)
20 JITCORE_PPC_REG_EXPAND(R19, 32)
21 JITCORE_PPC_REG_EXPAND(R20, 32)
22 JITCORE_PPC_REG_EXPAND(R21, 32)
23 JITCORE_PPC_REG_EXPAND(R22, 32)
24 JITCORE_PPC_REG_EXPAND(R23, 32)
25 JITCORE_PPC_REG_EXPAND(R24, 32)
26 JITCORE_PPC_REG_EXPAND(R25, 32)
27 JITCORE_PPC_REG_EXPAND(R26, 32)
28 JITCORE_PPC_REG_EXPAND(R27, 32)
29 JITCORE_PPC_REG_EXPAND(R28, 32)
30 JITCORE_PPC_REG_EXPAND(R29, 32)
31 JITCORE_PPC_REG_EXPAND(R30, 32)
32 JITCORE_PPC_REG_EXPAND(R31, 32)
33 
34 JITCORE_PPC_REG_EXPAND(PC, 32)
35 JITCORE_PPC_REG_EXPAND(LR, 32)
36 JITCORE_PPC_REG_EXPAND(CTR, 32)
37 JITCORE_PPC_REG_EXPAND(MSR, 32)
38 
39 JITCORE_PPC_REG_EXPAND(XER_SO, 32)
40 JITCORE_PPC_REG_EXPAND(XER_OV, 32)
41 JITCORE_PPC_REG_EXPAND(XER_CA, 32)
42 JITCORE_PPC_REG_EXPAND(XER_BC, 32)
43 
44 JITCORE_PPC_REG_EXPAND(CR0_LT, 8)
45 JITCORE_PPC_REG_EXPAND(CR0_GT, 8)
46 JITCORE_PPC_REG_EXPAND(CR0_EQ, 8)
47 JITCORE_PPC_REG_EXPAND(CR0_SO, 8)
48 JITCORE_PPC_REG_EXPAND(CR1_LT, 8)
49 JITCORE_PPC_REG_EXPAND(CR1_GT, 8)
50 JITCORE_PPC_REG_EXPAND(CR1_EQ, 8)
51 JITCORE_PPC_REG_EXPAND(CR1_SO, 8)
52 JITCORE_PPC_REG_EXPAND(CR2_LT, 8)
53 JITCORE_PPC_REG_EXPAND(CR2_GT, 8)
54 JITCORE_PPC_REG_EXPAND(CR2_EQ, 8)
55 JITCORE_PPC_REG_EXPAND(CR2_SO, 8)
56 JITCORE_PPC_REG_EXPAND(CR3_LT, 8)
57 JITCORE_PPC_REG_EXPAND(CR3_GT, 8)
58 JITCORE_PPC_REG_EXPAND(CR3_EQ, 8)
59 JITCORE_PPC_REG_EXPAND(CR3_SO, 8)
60 JITCORE_PPC_REG_EXPAND(CR4_LT, 8)
61 JITCORE_PPC_REG_EXPAND(CR4_GT, 8)
62 JITCORE_PPC_REG_EXPAND(CR4_EQ, 8)
63 JITCORE_PPC_REG_EXPAND(CR4_SO, 8)
64 JITCORE_PPC_REG_EXPAND(CR5_LT, 8)
65 JITCORE_PPC_REG_EXPAND(CR5_GT, 8)
66 JITCORE_PPC_REG_EXPAND(CR5_EQ, 8)
67 JITCORE_PPC_REG_EXPAND(CR5_SO, 8)
68 JITCORE_PPC_REG_EXPAND(CR6_LT, 8)
69 JITCORE_PPC_REG_EXPAND(CR6_GT, 8)
70 JITCORE_PPC_REG_EXPAND(CR6_EQ, 8)
71 JITCORE_PPC_REG_EXPAND(CR6_SO, 8)
72 JITCORE_PPC_REG_EXPAND(CR7_LT, 8)
73 JITCORE_PPC_REG_EXPAND(CR7_GT, 8)
74 JITCORE_PPC_REG_EXPAND(CR7_EQ, 8)
75 JITCORE_PPC_REG_EXPAND(CR7_SO, 8)
76 
77 JITCORE_PPC_REG_EXPAND(SPRG0, 32)
78 JITCORE_PPC_REG_EXPAND(SPRG1, 32)
79 JITCORE_PPC_REG_EXPAND(SPRG2, 32)
80 JITCORE_PPC_REG_EXPAND(SPRG3, 32)
81 JITCORE_PPC_REG_EXPAND(SRR0, 32)
82 JITCORE_PPC_REG_EXPAND(SRR1, 32)
83 JITCORE_PPC_REG_EXPAND(DAR, 32)
84 JITCORE_PPC_REG_EXPAND(DSISR, 32)
85 JITCORE_PPC_REG_EXPAND(PIR, 32)
86 JITCORE_PPC_REG_EXPAND(PVR, 32)
87 JITCORE_PPC_REG_EXPAND(DEC, 32)
88 JITCORE_PPC_REG_EXPAND(TBL, 32)
89 JITCORE_PPC_REG_EXPAND(TBU, 32)
90 
91 JITCORE_PPC_REG_EXPAND(SR0, 32)
92 JITCORE_PPC_REG_EXPAND(SR1, 32)
93 JITCORE_PPC_REG_EXPAND(SR2, 32)
94 JITCORE_PPC_REG_EXPAND(SR3, 32)
95 JITCORE_PPC_REG_EXPAND(SR4, 32)
96 JITCORE_PPC_REG_EXPAND(SR5, 32)
97 JITCORE_PPC_REG_EXPAND(SR6, 32)
98 JITCORE_PPC_REG_EXPAND(SR7, 32)
99 JITCORE_PPC_REG_EXPAND(SR8, 32)
100 JITCORE_PPC_REG_EXPAND(SR9, 32)
101 JITCORE_PPC_REG_EXPAND(SR10, 32)
102 JITCORE_PPC_REG_EXPAND(SR11, 32)
103 JITCORE_PPC_REG_EXPAND(SR12, 32)
104 JITCORE_PPC_REG_EXPAND(SR13, 32)
105 JITCORE_PPC_REG_EXPAND(SR14, 32)
106 JITCORE_PPC_REG_EXPAND(SR15, 32)
107 JITCORE_PPC_REG_EXPAND(IBAT0U, 32)
108 JITCORE_PPC_REG_EXPAND(IBAT0L, 32)
109 JITCORE_PPC_REG_EXPAND(IBAT1U, 32)
110 JITCORE_PPC_REG_EXPAND(IBAT1L, 32)
111 JITCORE_PPC_REG_EXPAND(IBAT2U, 32)
112 JITCORE_PPC_REG_EXPAND(IBAT2L, 32)
113 JITCORE_PPC_REG_EXPAND(IBAT3U, 32)
114 JITCORE_PPC_REG_EXPAND(IBAT3L, 32)
115 JITCORE_PPC_REG_EXPAND(DBAT0U, 32)
116 JITCORE_PPC_REG_EXPAND(DBAT0L, 32)
117 JITCORE_PPC_REG_EXPAND(DBAT1U, 32)
118 JITCORE_PPC_REG_EXPAND(DBAT1L, 32)
119 JITCORE_PPC_REG_EXPAND(DBAT2U, 32)
120 JITCORE_PPC_REG_EXPAND(DBAT2L, 32)
121 JITCORE_PPC_REG_EXPAND(DBAT3U, 32)
122 JITCORE_PPC_REG_EXPAND(DBAT3L, 32)
123 JITCORE_PPC_REG_EXPAND(SDR1, 32)
124 
125 JITCORE_PPC_REG_EXPAND(FPR0, 64)
126 JITCORE_PPC_REG_EXPAND(FPR1, 64)
127 JITCORE_PPC_REG_EXPAND(FPR2, 64)
128 JITCORE_PPC_REG_EXPAND(FPR3, 64)
129 JITCORE_PPC_REG_EXPAND(FPR4, 64)
130 JITCORE_PPC_REG_EXPAND(FPR5, 64)
131 JITCORE_PPC_REG_EXPAND(FPR6, 64)
132 JITCORE_PPC_REG_EXPAND(FPR7, 64)
133 JITCORE_PPC_REG_EXPAND(FPR8, 64)
134 JITCORE_PPC_REG_EXPAND(FPR9, 64)
135 JITCORE_PPC_REG_EXPAND(FPR10, 64)
136 JITCORE_PPC_REG_EXPAND(FPR11, 64)
137 JITCORE_PPC_REG_EXPAND(FPR12, 64)
138 JITCORE_PPC_REG_EXPAND(FPR13, 64)
139 JITCORE_PPC_REG_EXPAND(FPR14, 64)
140 JITCORE_PPC_REG_EXPAND(FPR15, 64)
141 JITCORE_PPC_REG_EXPAND(FPR16, 64)
142 JITCORE_PPC_REG_EXPAND(FPR17, 64)
143 JITCORE_PPC_REG_EXPAND(FPR18, 64)
144 JITCORE_PPC_REG_EXPAND(FPR19, 64)
145 JITCORE_PPC_REG_EXPAND(FPR20, 64)
146 JITCORE_PPC_REG_EXPAND(FPR21, 64)
147 JITCORE_PPC_REG_EXPAND(FPR22, 64)
148 JITCORE_PPC_REG_EXPAND(FPR23, 64)
149 JITCORE_PPC_REG_EXPAND(FPR24, 64)
150 JITCORE_PPC_REG_EXPAND(FPR25, 64)
151 JITCORE_PPC_REG_EXPAND(FPR26, 64)
152 JITCORE_PPC_REG_EXPAND(FPR27, 64)
153 JITCORE_PPC_REG_EXPAND(FPR28, 64)
154 JITCORE_PPC_REG_EXPAND(FPR29, 64)
155 JITCORE_PPC_REG_EXPAND(FPR30, 64)
156 JITCORE_PPC_REG_EXPAND(FPR31, 64)
157 JITCORE_PPC_REG_EXPAND(FPSCR, 32)
158 
159 JITCORE_PPC_REG_EXPAND(VR0, 128)
160 JITCORE_PPC_REG_EXPAND(VR1, 128)
161 JITCORE_PPC_REG_EXPAND(VR2, 128)
162 JITCORE_PPC_REG_EXPAND(VR3, 128)
163 JITCORE_PPC_REG_EXPAND(VR4, 128)
164 JITCORE_PPC_REG_EXPAND(VR5, 128)
165 JITCORE_PPC_REG_EXPAND(VR6, 128)
166 JITCORE_PPC_REG_EXPAND(VR7, 128)
167 JITCORE_PPC_REG_EXPAND(VR8, 128)
168 JITCORE_PPC_REG_EXPAND(VR9, 128)
169 JITCORE_PPC_REG_EXPAND(VR10, 128)
170 JITCORE_PPC_REG_EXPAND(VR11, 128)
171 JITCORE_PPC_REG_EXPAND(VR12, 128)
172 JITCORE_PPC_REG_EXPAND(VR13, 128)
173 JITCORE_PPC_REG_EXPAND(VR14, 128)
174 JITCORE_PPC_REG_EXPAND(VR15, 128)
175 JITCORE_PPC_REG_EXPAND(VR16, 128)
176 JITCORE_PPC_REG_EXPAND(VR17, 128)
177 JITCORE_PPC_REG_EXPAND(VR18, 128)
178 JITCORE_PPC_REG_EXPAND(VR19, 128)
179 JITCORE_PPC_REG_EXPAND(VR20, 128)
180 JITCORE_PPC_REG_EXPAND(VR21, 128)
181 JITCORE_PPC_REG_EXPAND(VR22, 128)
182 JITCORE_PPC_REG_EXPAND(VR23, 128)
183 JITCORE_PPC_REG_EXPAND(VR24, 128)
184 JITCORE_PPC_REG_EXPAND(VR25, 128)
185 JITCORE_PPC_REG_EXPAND(VR26, 128)
186 JITCORE_PPC_REG_EXPAND(VR27, 128)
187 JITCORE_PPC_REG_EXPAND(VR28, 128)
188 JITCORE_PPC_REG_EXPAND(VR29, 128)
189 JITCORE_PPC_REG_EXPAND(VR30, 128)
190 JITCORE_PPC_REG_EXPAND(VR31, 128)
191 JITCORE_PPC_REG_EXPAND(VRSAVE, 32)
192 JITCORE_PPC_REG_EXPAND(VSCR, 32)
miasm.arch.arm.regs.R8
list R8
Definition: regs.py:25
miasm.arch.msp430.regs.R14
list R14
Definition: regs.py:29
miasm.arch.arm.regs.R10
list R10
Definition: regs.py:27
miasm.arch.arm.regs.LR
list LR
Definition: regs.py:31
miasm.arch.arm.regs.R2
list R2
Definition: regs.py:19
miasm.arch.msp430.regs.R15
list R15
Definition: regs.py:30
miasm.arch.arm.regs.R0
list R0
Definition: regs.py:17
JITCORE_PPC_REG_EXPAND
#define JITCORE_PPC_REG_EXPAND(_name, _size)
Definition: JitCore_ppc32.c:191
miasm.arch.arm.regs.R11
list R11
Definition: regs.py:28
miasm.arch.arm.regs.R5
list R5
Definition: regs.py:22
miasm.arch.msp430.regs.R13
list R13
Definition: regs.py:28
miasm.arch.arm.regs.R9
list R9
Definition: regs.py:26
miasm.arch.arm.regs.R3
list R3
Definition: regs.py:20
miasm.arch.aarch64.regs.PC
PC
Definition: regs.py:137
miasm.arch.arm.regs.R1
list R1
Definition: regs.py:18
miasm.arch.arm.regs.R4
list R4
Definition: regs.py:21
miasm.arch.arm.regs.R6
list R6
Definition: regs.py:23
miasm.arch.arm.regs.R12
list R12
Definition: regs.py:29
miasm.arch.arm.regs.R7
list R7
Definition: regs.py:24