miasm.arch.x86.arch Namespace Reference

Classes
class	additional_info
class	bs_ad_mode
class	bs_cl1
class	bs_cond_disp
class	bs_cond_imm
class	bs_cond_imm64
class	bs_cond_index
class	bs_cond_scale
class	bs_cs
class	bs_disp
class	bs_ds
class	bs_eax
class	bs_edx
class	bs_es
class	bs_fbit
class	bs_fs
class	bs_gs
class	bs_mem
class	bs_modname_jecx
class	bs_modname_mode
class	bs_modname_size
class	bs_moff
class	bs_movoff
class	bs_msegoff
class	bs_op_mode
class	bs_op_mode64
class	bs_op_mode_no64
class	bs_op_modeno64
class	bs_reg
class	bs_rel_off
class	bs_rel_off08
class	bs_s08
class	bs_seg
class	bs_sib_base
class	bs_sib_index
class	bs_sib_scale
class	bs_ss
class	bs_st
class	field_size
class	group
class	instruction_x86
class	mn_x86
class	r_al
class	r_ax
class	r_cl
class	r_dx
class	r_eax
class	r_rax
class	x86_08
class	x86_08_ne
class	x86_16
class	x86_16_ne
class	x86_32
class	x86_32_ne
class	x86_64
class	x86_64_ne
class	x86_arg
class	x86_imm
class	x86_imm_fix_08
class	x86_reg
class	x86_reg_modrm
class	x86_reg_noarg
class	x86_reg_st
class	x86_rm_08
class	x86_rm_arg
class	x86_rm_bnd
class	x86_rm_bnd_m128
class	x86_rm_bnd_m64
class	x86_rm_bnd_reg
class	x86_rm_cr
class	x86_rm_dr
class	x86_rm_flt
class	x86_rm_m08
class	x86_rm_m16
class	x86_rm_m64
class	x86_rm_m80
class	x86_rm_mem
class	x86_rm_mem_far
class	x86_rm_mm
class	x86_rm_mm_m64
class	x86_rm_mm_reg
class	x86_rm_reg
class	x86_rm_reg_bnd
class	x86_rm_reg_m08
class	x86_rm_reg_m16
class	x86_rm_reg_mm
class	x86_rm_reg_noarg
class	x86_rm_reg_xmm
class	x86_rm_sd
class	x86_rm_segm
class	x86_rm_sx
class	x86_rm_sxd
class	x86_rm_w8
class	x86_rm_wd
class	x86_rm_xmm
class	x86_rm_xmm_m128
class	x86_rm_xmm_m32
class	x86_rm_xmm_m64
class	x86_rm_xmm_reg
class	x86_s08to16
class	x86_s08to32
class	x86_s08to64
class	x86_s32to64

Functions
def	is_op_segm (expr)
def	is_mem_segm (expr)
def	cb_deref_segmoff (tokens)
def	cb_deref_base_expr (tokens)
def	cb_deref_mem (tokens)
def	opmode_prefix (mode)
def	admode_prefix (mode)
def	v_opmode_info (size, opmode, rex_w, stk)
def	v_opmode (p)
def	v_admode_info (size, admode)
def	v_admode (p)
def	offsize (p)
def	get_prefix (s)
def	getmodrm (c)
def	setmodrm (mod, re, rm)
def	sib (c)
def	gen_modrm_form ()
def	exprfindmod (e, o=None)
def	test_addr_size (ptr, size)
def	parse_mem (expr, parent, w8, sx=0, xmm=0, mm=0, bnd=0)
def	expr2modrm (expr, parent, w8, sx=0, xmm=0, mm=0, bnd=0)
def	modrm2expr (modrm, parent, w8, sx=0, xmm=0, mm=0, bnd=0)
def	sib_cond (cls, mode, v)
def	rmmod (r, rm_arg_x=rm_arg, modrm=mod)
def	addop (name, fields, args=None, alias=False)
def	print_size (e)

Variables
	log = logging.getLogger("x86_arch")
	console_handler = logging.StreamHandler()
list	conditional_branch
list	unconditional_branch = ['JMP', 'JMPF']
string	f_isad = "AD"
string	f_s08 = "S08"
string	f_u08 = "U08"
string	f_s16 = "S16"
string	f_u16 = "U16"
string	f_s32 = "S32"
string	f_u32 = "U32"
string	f_s64 = "S64"
string	f_u64 = "U64"
string	f_imm = 'IMM'
dictionary	f_imm2size
dictionary	size2gpregs
dictionary	replace_regs64
dictionary	replace_regs32
dictionary	replace_regs16
dictionary	replace_regs
dictionary	segm2enc = {CS: 1, SS: 2, DS: 3, ES: 4, FS: 5, GS: 6}
	enc2segm = dict((value, key) for key, value in viewitems(segm2enc))
	segm_info = reg_info_dct(enc2segm)
dictionary	enc2crx
	crx_info = reg_info_dct(enc2crx)
dictionary	enc2drx
	drx_info = reg_info_dct(enc2drx)
	PLUS = Suppress("+")
	MULT = Suppress("*")
	COLON = Suppress(":")
	LBRACK = Suppress("[")
	RBRACK = Suppress("]")
tuple	gpreg
tuple	deref_mem_ad = (LBRACK + base_expr + RBRACK).setParseAction(cb_deref_base_expr)
tuple	deref_ptr = (base_expr + COLON + base_expr).setParseAction(cb_deref_segmoff)
	PTR = Suppress('PTR')
	FAR = Suppress('FAR')
	BYTE = Literal('BYTE')
	WORD = Literal('WORD')
	DWORD = Literal('DWORD')
	QWORD = Literal('QWORD')
	TBYTE = Literal('TBYTE')
	XMMWORD = Literal('XMMWORD')
dictionary	MEMPREFIX2SIZE
	SIZE2MEMPREFIX = dict((value, key) for key, value in viewitems(MEMPREFIX2SIZE))
tuple	mem_size = (BYTE | DWORD | QWORD | WORD | TBYTE | XMMWORD)
tuple	deref_mem = (mem_size + PTR + Optional((base_expr + COLON))+ deref_mem_ad).setParseAction(cb_deref_mem)
tuple	rmarg
tuple	mem_far = FAR + deref_mem
	cl_or_imm = r08_ecx.parser
dictionary	invmode = {16: 32, 32: 16}
list	repeat_mn
list	db_afs_64 = []
list	sib_64_s08_ebp = []
dictionary	SIZE2XMMREG
dictionary	SIZE2BNDREG
	d_rex_p = bs(l=0, cls=(bs_fbit,), fname="rex_p")
	d_rex_w = bs(l=0, cls=(bs_fbit,), fname="rex_w")
	d_rex_r = bs(l=0, cls=(bs_fbit,), fname="rex_r")
	d_rex_x = bs(l=0, cls=(bs_fbit,), fname="rex_x")
	d_rex_b = bs(l=0, cls=(bs_fbit,), fname="rex_b")
	d_g1 = bs(l=0, cls=(bs_fbit,), fname="g1")
	d_g2 = bs(l=0, cls=(bs_fbit,), fname="g2")
	d_cl1 = bs(l=1, cls=(bs_cl1,), fname="cl1")
	w8 = bs(l=1, fname="w8")
	se = bs(l=1, fname="se")
	sx = bs(l=0, fname="sx")
	sxd = bs(l=0, fname="sx")
	xmmreg = bs(l=0, fname="xmmreg")
	mmreg = bs(l=0, fname="mmreg")
	pref_f2 = bs(l=0, fname="prefixed", default=b"\xf2")
	pref_f3 = bs(l=0, fname="prefixed", default=b"\xf3")
	pref_66 = bs(l=0, fname="prefixed", default=b"\x66")
	no_xmm_pref = bs(l=0, fname="no_xmm_pref")
	no_rex = bs(l=0, fname="no_rex")
	sib_scale = bs(l=2, cls=(bs_cond_scale,), fname = "sib_scale")
	sib_index = bs(l=3, cls=(bs_cond_index,), fname = "sib_index")
	sib_base = bs(l=3, cls=(bs_cond_index,), fname = "sib_base")
	disp = bs(l=0, cls=(bs_cond_disp,), fname = "disp")
	s08 = bs(l=8, cls=(bs_s08, ))
	u08 = bs(l=8, cls=(x86_08, x86_arg))
	u07 = bs(l=7, cls=(x86_08, x86_arg))
	u16 = bs(l=16, cls=(x86_16, x86_arg))
	u32 = bs(l=32, cls=(x86_32, x86_arg))
	s3264 = bs(l=32, cls=(x86_s32to64, x86_arg))
	u08_3 = bs(l=0, cls=(x86_imm_fix_08, x86_arg), ival = 3)
	d0 = bs("000", fname='reg')
	d1 = bs("001", fname='reg')
	d2 = bs("010", fname='reg')
	d3 = bs("011", fname='reg')
	d4 = bs("100", fname='reg')
	d5 = bs("101", fname='reg')
	d6 = bs("110", fname='reg')
	d7 = bs("111", fname='reg')
	sd = bs(l=1, fname="sd")
	wd = bs(l=1, fname="wd")
	stk = bs(l=0, fname="stk")
	d_imm64 = bs(l=0, fname="imm64")
	d_eax = bs(l=0, cls=(bs_eax, ), fname='eax')
	d_edx = bs(l=0, cls=(bs_edx, ), fname='edx')
	d_st = bs(l=0, cls=(x86_reg_st, ), fname='st')
	d_imm = bs(l=0, cls=(bs_cond_imm,), fname="imm")
	d_ax = bs(l=0, cls=(r_ax, ), fname='ax')
	d_dx = bs(l=0, cls=(r_dx, ), fname='dx')
	d_cl = bs(l=0, cls=(r_cl, ), fname='cl')
	d_cs = bs(l=0, cls=(bs_cs, ), fname='cs')
	d_ds = bs(l=0, cls=(bs_ds, ), fname='ds')
	d_es = bs(l=0, cls=(bs_es, ), fname='es')
	d_ss = bs(l=0, cls=(bs_ss, ), fname='ss')
	d_fs = bs(l=0, cls=(bs_fs, ), fname='fs')
	d_gs = bs(l=0, cls=(bs_gs, ), fname='gs')
	rel_off = bs(l=0, cls=(bs_rel_off,), fname="off", order=-1)
	rel_off08 = bs(l=8, cls=(bs_rel_off08,), fname="off", order=-1)
	moff = bs(l=0, cls=(bs_moff,), fname="off")
	msegoff = bs(l=16, cls=(bs_msegoff,), fname="mseg")
	movoff = bs(l=0, cls=(bs_movoff,), fname="off")
	mod = bs(l=2, fname="mod")
	mod_mem = bs(l=2, cls=(bs_mem,), fname="mod")
	mod_reg = bs(l=2, cls=(bs_reg,), fname="mod")
	rmreg = bs(l=3, cls=(x86_rm_reg, ), order =1, fname = "reg")
	reg = bs(l=3, cls=(x86_reg, ), order =1, fname = "reg")
	reg_modrm = bs(l=3, cls=(x86_reg_modrm, ), order =1, fname = "reg")
	regnoarg = bs(l=3, default_val="000", order=1, fname="reg")
	segm = bs(l=3, cls=(x86_rm_segm, ), order =1, fname = "reg")
	crreg = bs(l=3, cls=(x86_rm_cr, ), order =1, fname = "reg")
	drreg = bs(l=3, cls=(x86_rm_dr, ), order =1, fname = "reg")
	mm_reg = bs(l=3, cls=(x86_rm_reg_mm, ), order =1, fname = "reg")
	xmm_reg = bs(l=3, cls=(x86_rm_reg_xmm, ), order =1, fname = "reg")
	bnd_reg = bs(l=3, cls=(x86_rm_reg_bnd, ), order =1, fname = "reg")
	fltreg = bs(l=3, cls=(x86_rm_flt, ), order =1, fname = "reg")
	rm = bs(l=3, fname="rm")
	rm_arg = bs(l=0, cls=(x86_rm_arg,), fname='rmarg')
	rm_arg_w8 = bs(l=0, cls=(x86_rm_w8,), fname='rmarg')
	rm_arg_sx = bs(l=0, cls=(x86_rm_sx,), fname='rmarg')
	rm_arg_sxd = bs(l=0, cls=(x86_rm_sxd,), fname='rmarg')
	rm_arg_sd = bs(l=0, cls=(x86_rm_sd,), fname='rmarg')
	rm_arg_wd = bs(l=0, cls=(x86_rm_wd,), fname='rmarg')
	rm_arg_08 = bs(l=0, cls=(x86_rm_08,), fname='rmarg')
	rm_arg_reg_m08 = bs(l=0, cls=(x86_rm_reg_m08,), fname='rmarg')
	rm_arg_reg_m16 = bs(l=0, cls=(x86_rm_reg_m16,), fname='rmarg')
	rm_arg_m08 = bs(l=0, cls=(x86_rm_m08,), fname='rmarg')
	rm_arg_m64 = bs(l=0, cls=(x86_rm_m64,), fname='rmarg')
	rm_arg_m80 = bs(l=0, cls=(x86_rm_m80,), fname='rmarg')
	rm_arg_m16 = bs(l=0, cls=(x86_rm_m16,), fname='rmarg')
	rm_mem = bs(l=0, cls=(x86_rm_mem,), fname='rmarg')
	rm_mem_far = bs(l=0, cls=(x86_rm_mem_far,), fname='rmarg')
	rm_arg_mm = bs(l=0, cls=(x86_rm_mm,), fname='rmarg')
	rm_arg_mm_m64 = bs(l=0, cls=(x86_rm_mm_m64,), fname='rmarg')
	rm_arg_mm_reg = bs(l=0, cls=(x86_rm_mm_reg,), fname='rmarg')
	rm_arg_xmm = bs(l=0, cls=(x86_rm_xmm,), fname='rmarg')
	rm_arg_xmm_m32 = bs(l=0, cls=(x86_rm_xmm_m32,), fname='rmarg')
	rm_arg_xmm_m64 = bs(l=0, cls=(x86_rm_xmm_m64,), fname='rmarg')
	rm_arg_xmm_m128 = bs(l=0, cls=(x86_rm_xmm_m128,), fname='rmarg')
	rm_arg_xmm_reg = bs(l=0, cls=(x86_rm_xmm_reg,), fname='rmarg')
	rm_arg_bnd = bs(l=0, cls=(x86_rm_bnd,), fname='rmarg')
	rm_arg_bnd_m64 = bs(l=0, cls=(x86_rm_bnd_m64,), fname='rmarg')
	rm_arg_bnd_m128 = bs(l=0, cls=(x86_rm_bnd_m128,), fname='rmarg')
	rm_arg_bnd_reg = bs(l=0, cls=(x86_rm_bnd_reg,), fname='rmarg')
	swapargs = bs_swapargs(l=1, fname="swap", mn_mod=list(range(1 << 1)))
	bs_opmode16 = bs(l=0, cls=(bs_op_mode,), mode = 16, fname="fopmode")
	bs_opmode32 = bs(l=0, cls=(bs_op_mode,), mode = 32, fname="fopmode")
	bs_opmode64 = bs(l=0, cls=(bs_op_mode,), mode = 64, fname="fopmode")
	bs_admode16 = bs(l=0, cls=(bs_ad_mode,), mode = 16, fname="fadmode")
	bs_admode32 = bs(l=0, cls=(bs_ad_mode,), mode = 32, fname="fadmode")
	bs_admode64 = bs(l=0, cls=(bs_ad_mode,), mode = 64, fname="fadmode")
	bs_opmode16_no64 = bs(l=0, cls=(bs_op_mode_no64,), mode = 16, fname="fopmode")
	bs_opmode32_no64 = bs(l=0, cls=(bs_op_mode_no64,), mode = 32, fname="fopmode")
	bs_mode64 = bs(l=0, cls=(bs_op_mode64,))
	bs_modeno64 = bs(l=0, cls=(bs_op_modeno64,))
list	cond_list
	cond = bs_mod_name(l=4, fname='cond', mn_mod=cond_list)
	bintree
	MMX/SSE/AVX operations  Categories are the same than here: https://software.intel.com/sites/landingpage/IntrinsicsGuide/. More...

Function Documentation

addop()

def miasm.arch.x86.arch.addop	(		name,
			fields,
			args = None,
			alias = False
	)

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admode_prefix()

def miasm.arch.x86.arch.admode_prefix

(

mode

)

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cb_deref_base_expr()

def miasm.arch.x86.arch.cb_deref_base_expr

(

tokens

)

cb_deref_mem()

def miasm.arch.x86.arch.cb_deref_mem

(

tokens

)

cb_deref_segmoff()

def miasm.arch.x86.arch.cb_deref_segmoff

(

tokens

)

expr2modrm()

def miasm.arch.x86.arch.expr2modrm	(		expr,
			parent,
			w8,
			sx = 0,
			xmm = 0,
			mm = 0,
			bnd = 0
	)

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exprfindmod()

def miasm.arch.x86.arch.exprfindmod	(		e,
			o = None
	)

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gen_modrm_form()

def miasm.arch.x86.arch.gen_modrm_form

(

)

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get_prefix()

def miasm.arch.x86.arch.get_prefix

(

s

)

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getmodrm()

def miasm.arch.x86.arch.getmodrm

(

c

)

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is_mem_segm()

def miasm.arch.x86.arch.is_mem_segm

(

expr

)

Returns True if is ExprMem and ptr is_op_segm

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is_op_segm()

def miasm.arch.x86.arch.is_op_segm

(

expr

)

Returns True if is ExprOp and op == 'segm'

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modrm2expr()

def miasm.arch.x86.arch.modrm2expr	(		modrm,
			parent,
			w8,
			sx = 0,
			xmm = 0,
			mm = 0,
			bnd = 0
	)

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offsize()

def miasm.arch.x86.arch.offsize

(

p

)

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opmode_prefix()

def miasm.arch.x86.arch.opmode_prefix

(

mode

)

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parse_mem()

def miasm.arch.x86.arch.parse_mem	(		expr,
			parent,
			w8,
			sx = 0,
			xmm = 0,
			mm = 0,
			bnd = 0
	)

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print_size()

def miasm.arch.x86.arch.print_size

(

e

)

rmmod()

def miasm.arch.x86.arch.rmmod	(		r,
			rm_arg_x = rm_arg,
			modrm = mod
	)

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setmodrm()

def miasm.arch.x86.arch.setmodrm	(		mod,
			re,
			rm
	)

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sib()

def miasm.arch.x86.arch.sib

(

c

)

sib_cond()

def miasm.arch.x86.arch.sib_cond	(		cls,
			mode,
			v
	)

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test_addr_size()

def miasm.arch.x86.arch.test_addr_size	(		ptr,
			size
	)

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v_admode()

def miasm.arch.x86.arch.v_admode

(

p

)

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v_admode_info()

def miasm.arch.x86.arch.v_admode_info	(		size,
			admode
	)

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v_opmode()

def miasm.arch.x86.arch.v_opmode

(

p

)

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v_opmode_info()

def miasm.arch.x86.arch.v_opmode_info	(		size,
			opmode,
			rex_w,
			stk
	)

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Variable Documentation

bintree

miasm.arch.x86.arch.bintree

MMX/SSE/AVX operations  Categories are the same than here: https://software.intel.com/sites/landingpage/IntrinsicsGuide/.

Arithmetic (integers)

Move SSE

Additions SSE

Substractions SSE

Arithmetic (floating-point)

Additions SSE

Substractions SSE

Multiplications SSE

Divisions SSE

Logical (floating-point)

XOR

AND

OR

AND MMX

ANDN MMX

OR MMX

XOR MMX

Comparisons (floating-point)

Convert SS = single precision SD = double precision

SS -> SD

bnd_reg

miasm.arch.x86.arch.bnd_reg = bs(l=3, cls=(x86_rm_reg_bnd, ), order =1, fname = "reg")

bs_admode16

miasm.arch.x86.arch.bs_admode16 = bs(l=0, cls=(bs_ad_mode,), mode = 16, fname="fadmode")

bs_admode32

miasm.arch.x86.arch.bs_admode32 = bs(l=0, cls=(bs_ad_mode,), mode = 32, fname="fadmode")

bs_admode64

miasm.arch.x86.arch.bs_admode64 = bs(l=0, cls=(bs_ad_mode,), mode = 64, fname="fadmode")

bs_mode64

miasm.arch.x86.arch.bs_mode64 = bs(l=0, cls=(bs_op_mode64,))

bs_modeno64

miasm.arch.x86.arch.bs_modeno64 = bs(l=0, cls=(bs_op_modeno64,))

bs_opmode16

miasm.arch.x86.arch.bs_opmode16 = bs(l=0, cls=(bs_op_mode,), mode = 16, fname="fopmode")

bs_opmode16_no64

miasm.arch.x86.arch.bs_opmode16_no64 = bs(l=0, cls=(bs_op_mode_no64,), mode = 16, fname="fopmode")

bs_opmode32

miasm.arch.x86.arch.bs_opmode32 = bs(l=0, cls=(bs_op_mode,), mode = 32, fname="fopmode")

bs_opmode32_no64

miasm.arch.x86.arch.bs_opmode32_no64 = bs(l=0, cls=(bs_op_mode_no64,), mode = 32, fname="fopmode")

bs_opmode64

miasm.arch.x86.arch.bs_opmode64 = bs(l=0, cls=(bs_op_mode,), mode = 64, fname="fopmode")

BYTE

miasm.arch.x86.arch.BYTE = Literal('BYTE')

cl_or_imm

miasm.arch.x86.arch.cl_or_imm = r08_ecx.parser

COLON

miasm.arch.x86.arch.COLON = Suppress(":")

cond

miasm.arch.x86.arch.cond = bs_mod_name(l=4, fname='cond', mn_mod=cond_list)

cond_list

list miasm.arch.x86.arch.cond_list

Initial value:

=  ["O", "NO", "B", "AE",
             "Z", "NZ", "BE", "A",
             "S", "NS", "PE", "NP",
             #"L", "NL", "NG", "G"]

conditional_branch

list miasm.arch.x86.arch.conditional_branch

Initial value:

=  ["JO", "JNO", "JB", "JAE",
                      "JZ", "JNZ", "JBE", "JA",
                      "JS", "JNS", "JPE", "JNP",
                      #"L", "NL", "NG", "G"]

console_handler

miasm.arch.x86.arch.console_handler = logging.StreamHandler()

crreg

miasm.arch.x86.arch.crreg = bs(l=3, cls=(x86_rm_cr, ), order =1, fname = "reg")

crx_info

miasm.arch.x86.arch.crx_info = reg_info_dct(enc2crx)

d0

miasm.arch.x86.arch.d0 = bs("000", fname='reg')

d1

miasm.arch.x86.arch.d1 = bs("001", fname='reg')

d2

miasm.arch.x86.arch.d2 = bs("010", fname='reg')

d3

miasm.arch.x86.arch.d3 = bs("011", fname='reg')

d4

miasm.arch.x86.arch.d4 = bs("100", fname='reg')

d5

miasm.arch.x86.arch.d5 = bs("101", fname='reg')

d6

miasm.arch.x86.arch.d6 = bs("110", fname='reg')

d7

miasm.arch.x86.arch.d7 = bs("111", fname='reg')

d_ax

miasm.arch.x86.arch.d_ax = bs(l=0, cls=(r_ax, ), fname='ax')

d_cl

miasm.arch.x86.arch.d_cl = bs(l=0, cls=(r_cl, ), fname='cl')

d_cl1

miasm.arch.x86.arch.d_cl1 = bs(l=1, cls=(bs_cl1,), fname="cl1")

d_cs

miasm.arch.x86.arch.d_cs = bs(l=0, cls=(bs_cs, ), fname='cs')

d_ds

miasm.arch.x86.arch.d_ds = bs(l=0, cls=(bs_ds, ), fname='ds')

d_dx

miasm.arch.x86.arch.d_dx = bs(l=0, cls=(r_dx, ), fname='dx')

d_eax

miasm.arch.x86.arch.d_eax = bs(l=0, cls=(bs_eax, ), fname='eax')

d_edx

miasm.arch.x86.arch.d_edx = bs(l=0, cls=(bs_edx, ), fname='edx')

d_es

miasm.arch.x86.arch.d_es = bs(l=0, cls=(bs_es, ), fname='es')

d_fs

miasm.arch.x86.arch.d_fs = bs(l=0, cls=(bs_fs, ), fname='fs')

d_g1

miasm.arch.x86.arch.d_g1 = bs(l=0, cls=(bs_fbit,), fname="g1")

d_g2

miasm.arch.x86.arch.d_g2 = bs(l=0, cls=(bs_fbit,), fname="g2")

d_gs

miasm.arch.x86.arch.d_gs = bs(l=0, cls=(bs_gs, ), fname='gs')

d_imm

miasm.arch.x86.arch.d_imm = bs(l=0, cls=(bs_cond_imm,), fname="imm")

d_imm64

miasm.arch.x86.arch.d_imm64 = bs(l=0, fname="imm64")

d_rex_b

miasm.arch.x86.arch.d_rex_b = bs(l=0, cls=(bs_fbit,), fname="rex_b")

d_rex_p

miasm.arch.x86.arch.d_rex_p = bs(l=0, cls=(bs_fbit,), fname="rex_p")

d_rex_r

miasm.arch.x86.arch.d_rex_r = bs(l=0, cls=(bs_fbit,), fname="rex_r")

d_rex_w

miasm.arch.x86.arch.d_rex_w = bs(l=0, cls=(bs_fbit,), fname="rex_w")

d_rex_x

miasm.arch.x86.arch.d_rex_x = bs(l=0, cls=(bs_fbit,), fname="rex_x")

d_ss

miasm.arch.x86.arch.d_ss = bs(l=0, cls=(bs_ss, ), fname='ss')

d_st

miasm.arch.x86.arch.d_st = bs(l=0, cls=(x86_reg_st, ), fname='st')

db_afs_64

list miasm.arch.x86.arch.db_afs_64 = []

deref_mem

tuple miasm.arch.x86.arch.deref_mem = (mem_size + PTR + Optional((base_expr + COLON))+ deref_mem_ad).setParseAction(cb_deref_mem)

deref_mem_ad

tuple miasm.arch.x86.arch.deref_mem_ad = (LBRACK + base_expr + RBRACK).setParseAction(cb_deref_base_expr)

deref_ptr

tuple miasm.arch.x86.arch.deref_ptr = (base_expr + COLON + base_expr).setParseAction(cb_deref_segmoff)

disp

miasm.arch.x86.arch.disp = bs(l=0, cls=(bs_cond_disp,), fname = "disp")

drreg

miasm.arch.x86.arch.drreg = bs(l=3, cls=(x86_rm_dr, ), order =1, fname = "reg")

drx_info

miasm.arch.x86.arch.drx_info = reg_info_dct(enc2drx)

DWORD

miasm.arch.x86.arch.DWORD = Literal('DWORD')

enc2crx

dictionary miasm.arch.x86.arch.enc2crx

Initial value:

=  {
    0: cr0,
    1: cr1,
    2: cr2,
    3: cr3,
    4: cr4,
    5: cr5,
    6: cr6,
    7: cr7,
}

enc2drx

dictionary miasm.arch.x86.arch.enc2drx

Initial value:

=  {
    0: dr0,
    1: dr1,
    2: dr2,
    3: dr3,
    4: dr4,
    5: dr5,
    6: dr6,
    7: dr7,
}

enc2segm

miasm.arch.x86.arch.enc2segm = dict((value, key) for key, value in viewitems(segm2enc))

f_imm

string miasm.arch.x86.arch.f_imm = 'IMM'

f_imm2size

dictionary miasm.arch.x86.arch.f_imm2size

Initial value:

=  {f_s08: 8, f_s16: 16, f_s32: 32, f_s64: 64,
              f_u08: 8, f_u16: 16, f_u32: 32, f_u64: 64}

f_isad

string miasm.arch.x86.arch.f_isad = "AD"

f_s08

string miasm.arch.x86.arch.f_s08 = "S08"

f_s16

string miasm.arch.x86.arch.f_s16 = "S16"

f_s32

string miasm.arch.x86.arch.f_s32 = "S32"

f_s64

string miasm.arch.x86.arch.f_s64 = "S64"

f_u08

string miasm.arch.x86.arch.f_u08 = "U08"

f_u16

string miasm.arch.x86.arch.f_u16 = "U16"

f_u32

string miasm.arch.x86.arch.f_u32 = "U32"

f_u64

string miasm.arch.x86.arch.f_u64 = "U64"

FAR

miasm.arch.x86.arch.FAR = Suppress('FAR')

fltreg

miasm.arch.x86.arch.fltreg = bs(l=3, cls=(x86_rm_flt, ), order =1, fname = "reg")

gpreg

tuple miasm.arch.x86.arch.gpreg

Initial value:

=  (
    gpregs08.parser |
    gpregs08_64.parser |
    gpregs16.parser |
    gpregs32.parser |
    gpregs64.parser |
    gpregs_xmm.parser |
    gpregs_mm.parser |
    gpregs_bnd.parser
)

invmode

dictionary miasm.arch.x86.arch.invmode = {16: 32, 32: 16}

LBRACK

miasm.arch.x86.arch.LBRACK = Suppress("[")

log

miasm.arch.x86.arch.log = logging.getLogger("x86_arch")

mem_far

tuple miasm.arch.x86.arch.mem_far = FAR + deref_mem

mem_size

tuple miasm.arch.x86.arch.mem_size = (BYTE | DWORD | QWORD | WORD | TBYTE | XMMWORD)

MEMPREFIX2SIZE

dictionary miasm.arch.x86.arch.MEMPREFIX2SIZE

Initial value:

=  {'BYTE': 8, 'WORD': 16, 'DWORD': 32,
                  'QWORD': 64, 'TBYTE': 80, 'XMMWORD': 128}

mm_reg

miasm.arch.x86.arch.mm_reg = bs(l=3, cls=(x86_rm_reg_mm, ), order =1, fname = "reg")

mmreg

miasm.arch.x86.arch.mmreg = bs(l=0, fname="mmreg")

mod

miasm.arch.x86.arch.mod = bs(l=2, fname="mod")

mod_mem

miasm.arch.x86.arch.mod_mem = bs(l=2, cls=(bs_mem,), fname="mod")

mod_reg

miasm.arch.x86.arch.mod_reg = bs(l=2, cls=(bs_reg,), fname="mod")

moff

miasm.arch.x86.arch.moff = bs(l=0, cls=(bs_moff,), fname="off")

movoff

miasm.arch.x86.arch.movoff = bs(l=0, cls=(bs_movoff,), fname="off")

msegoff

miasm.arch.x86.arch.msegoff = bs(l=16, cls=(bs_msegoff,), fname="mseg")

MULT

miasm.arch.x86.arch.MULT = Suppress("*")

no_rex

miasm.arch.x86.arch.no_rex = bs(l=0, fname="no_rex")

no_xmm_pref

miasm.arch.x86.arch.no_xmm_pref = bs(l=0, fname="no_xmm_pref")

PLUS

miasm.arch.x86.arch.PLUS = Suppress("+")

pref_66

miasm.arch.x86.arch.pref_66 = bs(l=0, fname="prefixed", default=b"\x66")

pref_f2

miasm.arch.x86.arch.pref_f2 = bs(l=0, fname="prefixed", default=b"\xf2")

pref_f3

miasm.arch.x86.arch.pref_f3 = bs(l=0, fname="prefixed", default=b"\xf3")

PTR

miasm.arch.x86.arch.PTR = Suppress('PTR')

QWORD

miasm.arch.x86.arch.QWORD = Literal('QWORD')

RBRACK

miasm.arch.x86.arch.RBRACK = Suppress("]")

reg

miasm.arch.x86.arch.reg = bs(l=3, cls=(x86_reg, ), order =1, fname = "reg")

reg_modrm

miasm.arch.x86.arch.reg_modrm = bs(l=3, cls=(x86_reg_modrm, ), order =1, fname = "reg")

regnoarg

miasm.arch.x86.arch.regnoarg = bs(l=3, default_val="000", order=1, fname="reg")

rel_off

miasm.arch.x86.arch.rel_off = bs(l=0, cls=(bs_rel_off,), fname="off", order=-1)

rel_off08

miasm.arch.x86.arch.rel_off08 = bs(l=8, cls=(bs_rel_off08,), fname="off", order=-1)

repeat_mn

list miasm.arch.x86.arch.repeat_mn

Initial value:

=  ["INS", "OUTS",
             "MOVSB", "MOVSW", "MOVSD", "MOVSQ",
             "SCASB", "SCASW", "SCASD", "SCASQ",
             "LODSB", "LODSW", "LODSD", "LODSQ",
             "STOSB", "STOSW", "STOSD", "STOSQ",
             "CMPSB", "CMPSW", "CMPSD", "CMPSQ",
             ]

replace_regs

dictionary miasm.arch.x86.arch.replace_regs

Initial value:

=  {16: replace_regs16,
                32: replace_regs32,
                64: replace_regs64}

replace_regs16

dictionary miasm.arch.x86.arch.replace_regs16

Initial value:

=  {
    AL: AX[:8],   CL: CX[:8],   DL: DX[:8],   BL: BX[:8],
    AH: AX[8:16], CH: CX[8:16], DH: DX[8:16], BH: BX[8:16],
 
    AX: AX[:16],  CX: CX[:16],  DX: DX[:16],  BX: BX[:16],
    SP: SP[:16],  BP: BP[:16],  SI: SI[:16],  DI: DI[:16],
 
 
    ExprId("ST", 64): float_st0,
    ExprId("ST(0)", 64): float_st0,
    ExprId("ST(1)", 64): float_st1,
    ExprId("ST(2)", 64): float_st2,
    ExprId("ST(3)", 64): float_st3,
    ExprId("ST(4)", 64): float_st4,
    ExprId("ST(5)", 64): float_st5,
    ExprId("ST(6)", 64): float_st6,
    ExprId("ST(7)", 64): float_st7,
 
}

replace_regs32

dictionary miasm.arch.x86.arch.replace_regs32

Initial value:

=  {
    AL: EAX[:8],   CL: ECX[:8],   DL: EDX[:8],   BL: EBX[:8],
    AH: EAX[8:16], CH: ECX[8:16], DH: EDX[8:16], BH: EBX[8:16],
 
    AX: EAX[:16], CX: ECX[:16], DX: EDX[:16], BX: EBX[:16],
    SP: ESP[:16], BP: EBP[:16], SI: ESI[:16], DI: EDI[:16],
 
    IP: EIP[:16],
 
 
    ExprId("ST", 64): float_st0,
    ExprId("ST(0)", 64): float_st0,
    ExprId("ST(1)", 64): float_st1,
    ExprId("ST(2)", 64): float_st2,
    ExprId("ST(3)", 64): float_st3,
    ExprId("ST(4)", 64): float_st4,
    ExprId("ST(5)", 64): float_st5,
    ExprId("ST(6)", 64): float_st6,
    ExprId("ST(7)", 64): float_st7,
 
}

replace_regs64

dictionary miasm.arch.x86.arch.replace_regs64

Initial value:

=  {
    AL: RAX[:8], CL: RCX[:8], DL: RDX[:8], BL: RBX[:8],
    AH: RAX[8:16], CH: RCX[8:16], DH: RDX[8:16], BH: RBX[8:16],
    SPL: RSP[0:8], BPL: RBP[0:8], SIL: RSI[0:8], DIL: RDI[0:8],
    R8B: R8[0:8], R9B: R9[0:8], R10B: R10[0:8], R11B: R11[0:8],
    R12B: R12[0:8], R13B: R13[0:8], R14B: R14[0:8], R15B: R15[0:8],
 
    AX: RAX[:16], CX: RCX[:16], DX: RDX[:16], BX: RBX[:16],
    SP: RSP[:16], BP: RBP[:16], SI: RSI[:16], DI: RDI[:16],
    R8W:  R8[:16], R9W:  R9[:16], R10W: R10[:16], R11W: R11[:16],
    R12W: R12[:16], R13W: R13[:16], R14W: R14[:16], R15W: R15[:16],
 
    EAX: RAX[:32], ECX: RCX[:32], EDX: RDX[:32], EBX: RBX[:32],
    ESP: RSP[:32], EBP: RBP[:32], ESI: RSI[:32], EDI: RDI[:32],
    R8D: R8[:32], R9D: R9[:32], R10D: R10[:32], R11D: R11[:32],
    R12D: R12[:32], R13D: R13[:32], R14D: R14[:32], R15D: R15[:32],
 
    IP: RIP[:16], EIP: RIP[:32],
 
    ExprId("ST", 64): float_st0,
    ExprId("ST(0)", 64): float_st0,
    ExprId("ST(1)", 64): float_st1,
    ExprId("ST(2)", 64): float_st2,
    ExprId("ST(3)", 64): float_st3,
    ExprId("ST(4)", 64): float_st4,
    ExprId("ST(5)", 64): float_st5,
    ExprId("ST(6)", 64): float_st6,
    ExprId("ST(7)", 64): float_st7,
 
}

rm

miasm.arch.x86.arch.rm = bs(l=3, fname="rm")

rm_arg

miasm.arch.x86.arch.rm_arg = bs(l=0, cls=(x86_rm_arg,), fname='rmarg')

rm_arg_08

miasm.arch.x86.arch.rm_arg_08 = bs(l=0, cls=(x86_rm_08,), fname='rmarg')

rm_arg_bnd

miasm.arch.x86.arch.rm_arg_bnd = bs(l=0, cls=(x86_rm_bnd,), fname='rmarg')

rm_arg_bnd_m128

miasm.arch.x86.arch.rm_arg_bnd_m128 = bs(l=0, cls=(x86_rm_bnd_m128,), fname='rmarg')

rm_arg_bnd_m64

miasm.arch.x86.arch.rm_arg_bnd_m64 = bs(l=0, cls=(x86_rm_bnd_m64,), fname='rmarg')

rm_arg_bnd_reg

miasm.arch.x86.arch.rm_arg_bnd_reg = bs(l=0, cls=(x86_rm_bnd_reg,), fname='rmarg')

rm_arg_m08

miasm.arch.x86.arch.rm_arg_m08 = bs(l=0, cls=(x86_rm_m08,), fname='rmarg')

rm_arg_m16

miasm.arch.x86.arch.rm_arg_m16 = bs(l=0, cls=(x86_rm_m16,), fname='rmarg')

rm_arg_m64

miasm.arch.x86.arch.rm_arg_m64 = bs(l=0, cls=(x86_rm_m64,), fname='rmarg')

rm_arg_m80

miasm.arch.x86.arch.rm_arg_m80 = bs(l=0, cls=(x86_rm_m80,), fname='rmarg')

rm_arg_mm

miasm.arch.x86.arch.rm_arg_mm = bs(l=0, cls=(x86_rm_mm,), fname='rmarg')

rm_arg_mm_m64

miasm.arch.x86.arch.rm_arg_mm_m64 = bs(l=0, cls=(x86_rm_mm_m64,), fname='rmarg')

rm_arg_mm_reg

miasm.arch.x86.arch.rm_arg_mm_reg = bs(l=0, cls=(x86_rm_mm_reg,), fname='rmarg')

rm_arg_reg_m08

miasm.arch.x86.arch.rm_arg_reg_m08 = bs(l=0, cls=(x86_rm_reg_m08,), fname='rmarg')

rm_arg_reg_m16

miasm.arch.x86.arch.rm_arg_reg_m16 = bs(l=0, cls=(x86_rm_reg_m16,), fname='rmarg')

rm_arg_sd

miasm.arch.x86.arch.rm_arg_sd = bs(l=0, cls=(x86_rm_sd,), fname='rmarg')

rm_arg_sx

miasm.arch.x86.arch.rm_arg_sx = bs(l=0, cls=(x86_rm_sx,), fname='rmarg')

rm_arg_sxd

miasm.arch.x86.arch.rm_arg_sxd = bs(l=0, cls=(x86_rm_sxd,), fname='rmarg')

rm_arg_w8

miasm.arch.x86.arch.rm_arg_w8 = bs(l=0, cls=(x86_rm_w8,), fname='rmarg')

rm_arg_wd

miasm.arch.x86.arch.rm_arg_wd = bs(l=0, cls=(x86_rm_wd,), fname='rmarg')

rm_arg_xmm

miasm.arch.x86.arch.rm_arg_xmm = bs(l=0, cls=(x86_rm_xmm,), fname='rmarg')

rm_arg_xmm_m128

miasm.arch.x86.arch.rm_arg_xmm_m128 = bs(l=0, cls=(x86_rm_xmm_m128,), fname='rmarg')

rm_arg_xmm_m32

miasm.arch.x86.arch.rm_arg_xmm_m32 = bs(l=0, cls=(x86_rm_xmm_m32,), fname='rmarg')

rm_arg_xmm_m64

miasm.arch.x86.arch.rm_arg_xmm_m64 = bs(l=0, cls=(x86_rm_xmm_m64,), fname='rmarg')

rm_arg_xmm_reg

miasm.arch.x86.arch.rm_arg_xmm_reg = bs(l=0, cls=(x86_rm_xmm_reg,), fname='rmarg')

rm_mem

miasm.arch.x86.arch.rm_mem = bs(l=0, cls=(x86_rm_mem,), fname='rmarg')

rm_mem_far

miasm.arch.x86.arch.rm_mem_far = bs(l=0, cls=(x86_rm_mem_far,), fname='rmarg')

rmarg

tuple miasm.arch.x86.arch.rmarg

Initial value:

=  (
    gpregs08.parser |
    gpregs08_64.parser |
    gpregs16.parser |
    gpregs32.parser |
    gpregs64.parser |
    gpregs_mm.parser |
    gpregs_xmm.parser |
    gpregs_bnd.parser
)

rmreg

miasm.arch.x86.arch.rmreg = bs(l=3, cls=(x86_rm_reg, ), order =1, fname = "reg")

s08

miasm.arch.x86.arch.s08 = bs(l=8, cls=(bs_s08, ))

s3264

miasm.arch.x86.arch.s3264 = bs(l=32, cls=(x86_s32to64, x86_arg))

sd

miasm.arch.x86.arch.sd = bs(l=1, fname="sd")

se

miasm.arch.x86.arch.se = bs(l=1, fname="se")

segm

miasm.arch.x86.arch.segm = bs(l=3, cls=(x86_rm_segm, ), order =1, fname = "reg")

segm2enc

dictionary miasm.arch.x86.arch.segm2enc = {CS: 1, SS: 2, DS: 3, ES: 4, FS: 5, GS: 6}

segm_info

miasm.arch.x86.arch.segm_info = reg_info_dct(enc2segm)

sib_64_s08_ebp

list miasm.arch.x86.arch.sib_64_s08_ebp = []

sib_base

miasm.arch.x86.arch.sib_base = bs(l=3, cls=(bs_cond_index,), fname = "sib_base")

sib_index

miasm.arch.x86.arch.sib_index = bs(l=3, cls=(bs_cond_index,), fname = "sib_index")

sib_scale

miasm.arch.x86.arch.sib_scale = bs(l=2, cls=(bs_cond_scale,), fname = "sib_scale")

SIZE2BNDREG

dictionary miasm.arch.x86.arch.SIZE2BNDREG

Initial value:

=  {64:gpregs_mm,
               128:gpregs_bnd}

size2gpregs

dictionary miasm.arch.x86.arch.size2gpregs

Initial value:

=  {8: gpregs08, 16: gpregs16,
               32: gpregs32, 64: gpregs64}

SIZE2MEMPREFIX

miasm.arch.x86.arch.SIZE2MEMPREFIX = dict((value, key) for key, value in viewitems(MEMPREFIX2SIZE))

SIZE2XMMREG

dictionary miasm.arch.x86.arch.SIZE2XMMREG

Initial value:

=  {64:gpregs_mm,
               128:gpregs_xmm}

stk

miasm.arch.x86.arch.stk = bs(l=0, fname="stk")

swapargs

miasm.arch.x86.arch.swapargs = bs_swapargs(l=1, fname="swap", mn_mod=list(range(1 << 1)))

sx

miasm.arch.x86.arch.sx = bs(l=0, fname="sx")

sxd

miasm.arch.x86.arch.sxd = bs(l=0, fname="sx")

TBYTE

miasm.arch.x86.arch.TBYTE = Literal('TBYTE')

u07

miasm.arch.x86.arch.u07 = bs(l=7, cls=(x86_08, x86_arg))

u08

miasm.arch.x86.arch.u08 = bs(l=8, cls=(x86_08, x86_arg))

u08_3

miasm.arch.x86.arch.u08_3 = bs(l=0, cls=(x86_imm_fix_08, x86_arg), ival = 3)

u16

miasm.arch.x86.arch.u16 = bs(l=16, cls=(x86_16, x86_arg))

u32

miasm.arch.x86.arch.u32 = bs(l=32, cls=(x86_32, x86_arg))

unconditional_branch

list miasm.arch.x86.arch.unconditional_branch = ['JMP', 'JMPF']

w8

miasm.arch.x86.arch.w8 = bs(l=1, fname="w8")

wd

miasm.arch.x86.arch.wd = bs(l=1, fname="wd")

WORD

miasm.arch.x86.arch.WORD = Literal('WORD')

xmm_reg

miasm.arch.x86.arch.xmm_reg = bs(l=3, cls=(x86_rm_reg_xmm, ), order =1, fname = "reg")

xmmreg

miasm.arch.x86.arch.xmmreg = bs(l=0, fname="xmmreg")

XMMWORD

miasm.arch.x86.arch.XMMWORD = Literal('XMMWORD')